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dual, 16 - /12 - bit nano dac+ with spi interface data sheet ad5689 / AD5687 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no licen se is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.3 29.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features high relative accuracy (inl): 2 lsb maximum at 16 bits tiny package: 3 mm 3 mm, 16 - lead lfcsp tue : 0.1% of fsr maximum offset error: 1.5 mv maximum gain error: 0.1% of fsr maximum high drive capability: 20 ma, 0.5 v from supply rails user - selectable gain of 1 or 2 (gain pin) reset to zero scale or midscale (rstsel pin) 1.8 v logic compatibility 50 mhz spi with readback or daisy chain low glitch: 0.5 nv - sec robust 4 k v hbm and 1.5 kv ficdm esd ratings low power: 3.3 mw at 3 v 2.7 v to 5.5 v power supply ? 40c to +105c temperature range applications optical transceivers base station power amplifiers process control (plc i/o cards) industrial automation data acquisition systems functional block dia gram figure 1. general description the ad5689 / AD5687 member s of the nano dac+? family are low power, dual, 16 - /12 - bit , buffered voltage output digital - to - analog converters ( dacs ) . the devices include a gain select pin giving a full - scale output of 2.5 v (gain = 1) or 5 v (gain = 2). the ad5689 / AD5687 operate from a single 2.7 v to 5.5 v supply, are guaranteed monotonic by design, and exhibit less than 0.1% fsr gain error and 1.5 mv offset error performance. both devices are available in a 3 mm 3 mm lfcsp and a tssop package. the ad5689 / AD5687 also incorporate a power - on reset circuit and a rstsel pin that ensure that the dac outputs power up to zero scale or midscale and remain there until a va lid write takes place. each part contains a per channel power - down feature that reduces the current consumption of the device to 4 a at 3 v while in power - down mode. the ad5689 / AD5687 use a versatile serial peripheral interface that operates at clock rates up to 50 mhz . both devices contain a v logic pin that is intended for 1.8 v/3 v/5 v logic. table 1 . related de vices interface reference 16 - bit 12- bit spi internal ad5689r AD5687r external ad5689 AD5687 i 2 c internal n/a ad5697 r external n/a n/a product highlights 1. high relative accuracy (inl) . ad5689 (16 - bit): 2 lsb maximum AD5687 (12 - bit): 1 lsb maximum 2. excellent dc performance. total unadjusted error: 0.1% of fsr maximum offset error: 1.5 mv maximum gain error: 0.1% of fsr maximum 3. two package options. 3 mm 3 mm, 16 - lead lfcsp 16- lead tssop sclk v logic sync sdin sdo input register dac register string dac a buffer v out a input register dac register string dac b buffer v out b v ref gnd v dd power- down logic power-on reset gain = 1/2 interface logic rstsel gain ldac reset ad5689/AD5687 1 1255-001
ad5689/AD5687 data sheet rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 4 timing cha racteristics ................................................................ 5 daisy -c hain and readback timing characteristics ................ 6 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 15 theory of operation ...................................................................... 17 digital - to - analog converters (dacs) .................................... 17 transfer function ....................................................................... 17 dac architecture ....................................................................... 17 serial interface ............................................................................ 18 standalone o peration ................................................................ 19 write and update commands .................................................. 19 daisy - chain operation ............................................................. 19 readback operation .................................................................. 20 power - down operation ............................................................ 20 load dac (hardware ldac pin) ........................................... 21 ldac mask register ................................................................. 21 hardware reset ( reset ) .......................................................... 22 reset select pin (rstsel) ........................................................ 22 applications information .............................................................. 23 microprocessor interfacing ....................................................... 23 ad 5689/AD5687 to adsp - bf531 interface ........................... 23 ad5689/AD5687 to sport interface ...................................... 23 layout guidelines ....................................................................... 23 galvanically isolated interface ................................................. 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 2/ 13 revision 0: initial version
data sheet ad5689/AD5687 rev. 0 | page 3 of 24 specifications v dd = 2.7 v to 5.5 v; 1.8 v v logic 5.5 v ; a ll specifications t min to t max , unless otherwise noted. r l = 2 k?; c l = 200 pf. table 2. parameter min typ max unit test conditions/comments static performance 1 ad5689 resolution 16 bits relative accuracy 1 2 lsb gain = 2 1 3 gain = 1 differential nonlinearity 1 lsb guaranteed monotonic by design AD5687 resolution 12 bits relative accuracy 0.12 1 lsb differential nonlinearity 1 lsb guaranteed monotonic by design zero - code error 0.4 1.5 mv all 0 s loaded to dac register offset error +0.1 1.5 mv full - scale error +0.01 0.1 % of fsr all 1 s loaded to dac register gain error 0.02 0.1 % of fsr total unadjusted error 0.01 0.1 % of fsr gain = 2; tssop 0.2 % of fsr gain = 1; tssop offset error drift 2 1 v/c gain temperature coefficient 2 1 ppm of fsr/c dc power supply rejection ratio 2 0.15 mv/v dac code = midscale, v dd = 5 v 10 % dc crosstalk 2 2 v due to single - channel, full - scale output change 3 v/ma due to load current change 2 v due to powering down (per chan nel) output characteristics 2 output voltage range 0 v ref v gain = 1 0 2 v ref v gain = 2 ; see figure 23 capacitive load stability 2 nf r l = 10 nf r l = 1 k resistive load 3 1 k load regulation 80 v/ma 5 v 10%, dac code = midscale; ? 30 ma i out 30 ma 80 v/ma 3 v 10%, dac code = midscale; ? 20 ma i out 20 ma short - circuit current 4 40 ma load impedance at rails 5 25 see figure 23 power - up time 2.5 s coming out of power - down mode; v dd = 5 v reference input reference current 6 90 a v ref = v dd = v logic =5.5 v, g ain = 1 180 a v ref = v dd = v logic =5.5 v, g ain = 2 reference input range 1 v dd v gain = 1 1 v dd /2 v gain = 2 reference input impedance 16 k gain = 1 32 k gain = 2 logic inputs 2 input current 2 a per pin input low voltage (v inl ) 0.3 v logic v input high voltage (v inh ) 0.7 v logic v pin capacitance 2 pf
ad5689/AD5687 data sheet rev. 0 | page 4 of 24 parameter min typ max unit test conditions/comments logic outputs (sdo) 2 output low voltage (v ol ) 0.4 v i sink = 200 a output high voltage (v oh ) v logic ? 0.4 v i source = 200 a floating state output capacitance 4 pf power requirements v logic 1.8 5.5 v i logic 3 a v dd 2.7 5.5 v gain = 1 v dd v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 7 0.59 0.7 ma all power - down modes 8 1 4 a ? 40c to +85c 6 a ? 40c to +105c 1 dc specifications tested with the outputs unloaded, unless otherwise noted. upper dead band = 10 mv ; it exists only when v ref = v dd with gain = 1 or when v ref /2 = v dd with gain = 2. linearity is calculated using a reduced code range of 256 to 65 , 280 ( ad5689 ) and 12 to 4080 ( AD5687 ). 2 guaranteed by design and characterization ; not production tested. 3 channel a can have an output current of up to 30 ma. similarly, channel b can have an output current of up to 30 ma , up to a junction temperature of 110c. 4 v dd = 5 v . the device s include current limiting that is intended to protect them during tempor ary overload conditions. junction temperature may be exc eed ed during current limit, but o peration above the specified max imum operation junction temperature can impair device reliability. 5 when drawing a load current at either rail, the output voltage headroom , with respect t o that rail, is limited by the 25 typical c hannel res istance of th e output devices. for example , when sinking 1 m a, the minimum output voltage = 25 1 ma = 25 mv ( see figure 23) . 6 initial accuracy presolder reflow is 750 v; ou tput voltage includes the effects of preconditioning drift. 7 interface inactive. both dacs active. dac outputs unloaded. 8 both dacs powered down. ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; 1.8 v v logic 5.5 v ; all specifications t min to t max , unless otherwise noted. temperature range = ?40c to +105c, typical at 25c. guaranteed by design and characterization, not production tested. table 3 . parameter 1 min typ max unit test conditions/comments output voltage settling time ad5689 5 8 s ? to ? scale settling to 2 lsb AD5687 5 7 s ? to ? scale settling to 2 lsb slew rate 0.8 v/s digital - to - analog glitch impulse 0.5 nv - sec 1 lsb change around major carry digital feedthrough 0.13 nv - sec digital crosstalk 0.1 nv - sec analog crosstalk 0.2 nv - sec dac -to - dac crosstalk 0.3 nv -s ec total harmonic distortion (thd) 2 ? 80 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz output noise spectral density (nsd) 300 nv/ hz dac code = midscale, 10 khz , gain = 2 output noise 6 v p -p 0.1 hz to 10 hz s ignal - to - noise ratio (snr) 90 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz spurious free dynamic range ( sfdr ) 83 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz signal - to - noise - and - distortion ratio ( sinad ) 80 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz 1 see the terminology section. 2 digitally generated sine wave at 1 khz.
data sheet ad5689/AD5687 rev. 0 | page 5 of 24 timing characteristi cs all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 2 . v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v; v ref = 2.5 v. all specifications t min to t max , unless otherwise noted. table 4. 1.8 v v logic < 2.7 v 2.7 v v logic 5.5 v parameter 1 min max min max unit description t 1 33 20 ns sclk cycle t ime t 2 16 10 ns sclk high t ime t 3 16 10 ns sclk low t ime t 4 15 10 ns sync to sclk falling edge setup t ime t 5 5 5 ns data setup t ime t 6 5 5 ns data hold t ime t 7 15 10 ns sclk falling e dge to sync rising e dge t 8 20 20 ns minimum sync high time (update single channel or both channels) t 9 16 10 ns sync f all ing edge to sclk fall i gnore t 10 25 15 ns ldac pulse width l ow t 11 30 20 ns sclk falling e dge to ldac rising e dge t 12 20 20 ns sclk falling e dge to ldac falling e dge t 13 30 30 ns reset minimum pulse width l ow t 14 30 30 ns reset pulse activation t ime power - up time 4.5 4.5 s time that is required to exit power - down mode and enter normal mode of operation; 24 th clock ed ge to 90% of dac midscale value with output unloaded 1 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v, 2.7 v v logic v dd . guaranteed by design and characterization; not production tested. figure 2. serial write operation t 4 t 3 sclk sync sdin t 1 t 2 t 5 t 6 t 7 t 8 db23 t 9 t 10 t 11 ldac 1 ldac 2 t 12 1 asynchronous ldac update mode. 2 synchronous ldac update mode. reset t 13 t 14 v out x db0 1 1255-002
ad5689/AD5687 data sheet rev. 0 | page 6 of 24 daisy -c hain and readback timing characteristics all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 4 and figure 5 . v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v, v ref = 2.5 v. all specifications t min to t max , unless otherwise noted. v dd = 2.7 v to 5.5 v. table 5. 1.8 v v logic < 2.7 v 2.7 v v logic 5.5 v unit parameter 1 min max min max description t 1 66 40 ns sclk cycle t ime t 2 33 20 ns sclk high t ime t 3 33 20 ns sclk low t ime t 4 33 20 ns sync to sclk falling edge t 5 5 5 ns data setup t ime t 6 5 5 ns data hold t ime t 7 15 10 ns sclk falling e dge to sync rising e dge t 8 60 30 ns minimum sync high time t 9 60 30 ns minimum sync h igh t ime t 10 36 25 ns sdo data v alid from sclk rising e dge t 11 15 10 ns sclk falling e dge to sync rising e dge t 12 15 10 ns sync rising edge to sclk rising e dge 1 maximum sclk frequency is 25 mhz or 15 mhz at v dd = 2.7 v to 5.5 v, 1.8 v v logic v dd . guaranteed by design and characterization; not production tested. circuit and timing diagrams figure 3. load circuit for digital output (sdo) timing specifications figure 4. daisy - chain timing diagram 200a i ol 200a i oh v oh (min) to output pin c l 20pf 1 1255-003 t 4 t 5 t 6 t 8 sdo sdin sync sclk 48 24 db23 db0 db23 db0 db23 input word for dac n undefined input word for dac n + 1 input word for dac n db 0 t 11 t 12 t 10 1 1255-004
data sheet ad5689/AD5687 rev. 0 | page 7 of 24 figure 5 . readback timing diagram sync t 8 t 6 sclk 24 1 24 1 t 9 t 4 t 2 t 7 t 3 t 1 db23 db0 db23 db0 sdin nop condition input word specifies register to be read t 5 db23 db0 db23 db0 sdo selected register data clocked out undefined t 10 1 1255-005
ad5689/AD5687 data sheet rev. 0 | page 8 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to gnd ? 0.3 v to +7 v v logic to gnd ? 0.3 v to +7 v v out to gnd ? 0.3 v to v dd + 0.3 v v ref to gnd ? 0.3 v to v dd + 0.3 v digital input voltage to gnd ? 0.3 v to v logic + 0.3 v operating temperature range ? 40c to +10 5c storage temperature range ? 65c to +150c junction temperature 125c 16 - lead tssop, ja thermal impedance, 0 airflow ( 4- layer board) 1 12.6 c/w 16 - lead lfcsp, ja thermal impedance, 0 airflow ( 4- layer board) 70 c/w reflow soldering peak temperature, pb free (j - std - 020) 260c esd 1 4 kv ficdm 1.5 kv 1 human body model (hbm) classification. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad5689/AD5687 rev. 0 | page 9 of 24 pin configurations and function descript ions figure 6. 16 - lead lfcsp pin configuration figure 7. 16 - lead tssop pin configuration table 7. pin function descriptions pin no. mnemonic description lfcsp tssop 1 3 v out a analog output voltage from dac a. the output amplifier has rail -to - rail operation. 2 4 gnd ground reference point for all circuitry on the ad5689 / AD5687 . 3 5 v dd power supply input. the ad5689 / AD5687 can be operate d from 2.7 v to 5.5 v. decouple the supply with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 2 nc no connect. do not connect to this pin. 5 7 v out b analog output voltage from dac b . the output amplifier has rail -to - rail operation. 6 8 sdo serial data output. sdo c an be used to daisy - chain a number of ad5689 / AD5687 devices together , or it can be used for readback. the serial data is transferred on the rising edge of sclk and is valid on the falling edge of the clock. 7 9 ldac ldac can be operated in two modes: asynchronous and synchronous. pulsing this pin low allows either or both dac registers to be updated if the input registers have new data; both dac outputs can be update d simultaneously. this pin can also be tied permanently low . 8 10 gain gain select . when this pin is tied to gnd , both dac s output a span from 0 v to v ref . if this pin is tied to v logic , both dac s output a span of 0 v to 2 v ref . 9 11 v logic digital power supply. voltage ranges from 1.8 v to 5.5 v. 10 12 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates of up to 50 mhz. 11 13 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, d ata is transferred in on the falling edges of the next 24 clocks. 12 14 sdin serial data input. this device has a 24 - bit input shift register. data is clocked into the register on the falling edge of the serial clock inpu t. 13 15 reset asynchronous reset input. the reset input i s falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset is activated, the input register and the dac register are updated with zero scale or mid scale , depending on the state of the rstsel pin. 14 16 rstsel power - on reset select. tying this pin to gnd powers up both dacs to zero scale. tying this pin to v logic powers up both dacs to midscale. 15 1 v ref reference input voltage. 16 6 nc no connect. do not connect to this pin. 17 n/a epad exposed pad. the exposed pad must be tied to gnd. 12 11 10 1 3 4 sdin sync sclk 9 v logic v out a v dd 2 gnd nc 6 sdo 5 v out b 7 ldac 8 gain 16 nc 15 v ref 14 rstsel 13 reset notes 1. nc = no connect. do not connect to this pin. 2. the exposed pad must be tied to gnd. top view (not to scale) ad5689/ AD5687 1 1255-006 1 2 3 4 5 6 7 8 nc v out a gnd v out b nc v dd v ref sdo 16 15 14 13 12 11 10 9 reset sdin sync gain ldac v logic sclk rstsel notes 1. nc = no connect. do not connect to this pin. top view (not to scale) ad5689/ AD5687 1 1255-007
ad5689/AD5687 data sheet rev. 0 | page 10 of 24 typical performance characteristics figure 8. ad5689 integral nonlinearity (inl) vs. code figure 9. ad5689 differential nonlinearity ( dnl ) vs. code figure 10 . inl error and dnl error vs. temperature figure 11 . AD5687 inl vs. code figure 12 . AD5687 dnl vs. code figure 13 . inl error and dnl error vs. v ref 10 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 0 10000 20000 30000 40000 50000 60000 inl (lsb) code v dd = 5v t a = 25c reference = 2.5v 1 1255-008 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 0 10000 20000 30000 40000 50000 60000 dnl (lsb) code v dd = 5v t a = 25c reference = 2.5v 1 1255-010 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?40 110 60 10 error (lsb) temperature (c) inl dnl v dd = 5v t a = 25c reference = 2.5v 1 1255-012 10 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 0 625 1250 1875 2500 3125 3750 4096 inl (lsb) code v dd = 5v t a = 25c reference = 2.5v 1 1255-009 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 0 625 1250 1875 2500 3125 3750 4096 dnl (lsb) code v dd = 5v t a = 25c reference = 2.5v 1 1255-0 11 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 0 5.04.54.03.53.02.52.01.51.00.5 error (lsb) v ref (v) inl dnl v dd = 5v t a = 25c reference = 2.5v 1 1255-013
data sheet ad5689/AD5687 rev. 0 | page 11 of 24 figure 14 . inl error and dnl error vs. supply voltage figure 15 . gain error and full - scale error vs. temperature figure 16 . zero - code error and offset error vs. temperature figure 17 . gain error and full - scale error vs. supply voltage figure 18 . zero - code error and offset error vs. supply voltage figure 19 . total unadjusted error ( tue ) vs. temperature 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 2.7 5.2 4.7 4.2 3.7 3.2 error (lsb) supply voltage (v) inl dnl v dd = 5v t a = 25c reference = 2.5v 1 1255-014 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temperature (c) gain error full-scale error v dd = 5v t a = 25c reference = 2.5v 1 1255-015 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 ?20 0 20 40 60 80 100 120 error (mv) temperature (c) offset error zero-code error v dd = 5v t a = 25c reference = 2.5v 1 1255-016 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 2.7 5.2 4.7 4.2 3.7 3.2 error (% of fsr) supply voltage (v) gain error full-scale error v dd = 5v t a = 25c reference = 2.5v 1 1255-017 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 2.7 5.2 4.7 4.2 3.7 3.2 error (mv) supply voltage (v) zero-code error offset error v dd = 5v t a = 25c internal reference = 2.5v 1 1255-018 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 ?40 ?20 0 20 40 60 80 100 120 total unadjusted error (% of fsr) temperature (c) v dd = 5v t a = 25c internal reference = 2.5v 1 1255-019
ad5689/AD5687 data sheet rev. 0 | page 12 of 24 figure 20 . tue vs. supply voltage , gain = 1 figure 21 . tue vs. code figure 22 . i dd histogram figure 23 . headroom/footroom vs. load current figure 24 . source and sink capability at 5 v figure 25 . source and sink capability at 3 v 0.10 0.08 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 2.7 5.2 4.7 4.2 3.7 3.2 total unadjusted error (% of fsr) supply voltage (v) v dd = 5v t a = 25c internal reference = 2.5v 1 1255-020 0 ?0.01 ?0.02 ?0.03 ?0.04 ?0.05 ?0.06 ?0.07 ?0.08 ?0.09 ?0.10 0 10000 20000 30000 40000 50000 60000 65535 total unadjusted error (% of fsr) code v dd = 5v t a = 25c internal reference = 2.5v 1 1255-021 25 20 15 10 5 0 540 560 580 600 620 640 hits i dd full scale (v) v dd = 5v t a = 25c external reference = 2.5v 1 1255-022 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 5 10 15 20 25 30 v out (v) load current (ma) sourcing 2.7v sourcing 5v sinking 2.7v sinking 5v 1 1255-023 7 ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) full scale one-quarter scale midscale three-quarter scale zero scale v dd = 5v t a = 25c gain = 2 internal reference = 2.5v 1 1255-024 1 1255-025 5 ?2 ?1 0 1 2 3 4 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) v dd = 3v t a = 25c external reference = 2.5v gain = 1 full scale one-quarter scale midscale three-quarter scale zero scale
data sheet ad5689/AD5687 rev. 0 | page 13 of 24 figure 26 . supply current vs. temperature figure 27 . settling time, 5 v figure 28 . power - on reset to 0 v figure 29 . exiting power - down to midscale figure 30 . digital -to- analog glitch impulse figure 31 . analog crosstalk, channel a 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?40 110 60 10 supply current (ma) temperature (c) full scale 1 1255-026 0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 10 320 160 40 80 20 v out (v) time (s) dac a dac b v dd = 5v t a = 25c reference = 2.5v ? to ? scale 1 1255-027 ?0.01 0 0.06 0.01 0.02 0.03 0.04 0.05 ?1 0 6 1 2 3 4 5 ?10 15 10 0 5 ?5 v out (v) v dd (v) time (s) channel b v dd channel a t a = 25c reference = 2.5v 1 1255-028 0 1 3 2 ?5 10 0 5 v out (v) time (s) sync channel a channel b v dd = 5v t a = 25c reference = 2.5v gain = 1 gain = 2 1 1255-029 2.4988 2.5008 2.5003 2.4998 2.4993 0 12 8 10 4 6 2 v out (v) time (s) channel b t a = 25c v dd = 5.25v reference = 2.5v positive major code transition energy = 0.227206nv-sec 1 1255-030 ?0.002 ?0.001 0 0.001 0.002 0.003 0 25 20 10 15 5 v out ac-coupled (v) time (s) 1 1255-031 channel b
ad5689/AD5687 data sheet rev. 0 | page 14 of 24 figure 32 . 0.1 hz to 10 hz output noise plot figure 33 . total harmonic distortion at 1 khz figure 34 . settling time vs. capacitive load figure 35 . multiplying bandwidth, reference = 2.5 v, 0.1 v p - p, 10 khz to 10 mhz ch1 10v m1.0s a ch1 802mv 1 t v dd = 5v t a = 25c reference = 2.5v 1 1255-032 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 20000 16000 8000 12000 4000 2000 18000 10000 14000 6000 thd (dbv) frequency (hz) v dd = 5v t a = 25c reference = 2.5v 1 1255-033 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 1.590 1.630 1.620 1.600 1.610 1.625 1.605 1.615 1.595 v out (v) time (ms) 0nf 0.1nf 10nf 0.22nf 4.7nf v dd = 5v t a = 25c reference = 2.5v 1 1255-034 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 10m 1m 100k bandwidth (db) frequency (hz) v dd = 5v t a = 25c reference = 2.5v, 0.1v p-p 1 1255-035
data sheet ad5689/AD5687 rev. 0 | page 15 of 24 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. t ypical inl vs. code plot s are shown figure 8 and figure 11. differential nonlinearity (dnl) differential nonlinearity is the difference betwee n the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. t ypical dnl vs. code plot s are shown in figure 9 and figure 12. zero - code error zero - code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero - code error is always po sitive in the device because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero - code error is expressed in mv. a plot of zero - code error vs. temperature is shown in figure 16 . full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 l sb. full - scale error is expressed in percent of full - scale range (% of fsr) . a plot of full - scale error vs. temperature is shown in figure 15 . gain error gain error i s a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal and is expressed as % of fsr. offset error drift offset error drift is a measurement of the change in offset error with a change in te mperature. it is expressed in v/c. gain temperature coefficient gain temperature coefficient is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the device with code 512 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by change s in the supply voltage. it is the ratio of the change in v out to a change in v dd for the full - scale output of the dac. it is measured in mv/v . v ref is held at 2 v, and v dd is varied by 10%. output voltage settling time output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input ch ange and is measured from the rising edge of sync . digit al -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv -s ec and is measured when the digital input code is changed by 1 lsb at the major carry transition , that is, 0x7fff to 0x8000 (see figure 30). digital feedthrough digital feedthrou gh is a measure of the i mpulse injected into the analog output of the dac from the digital inputs of the dac, but it is measured when the dac output is not updated. it is specified in nv -s ec and measured with a full - scale code change on the data bus, that is, from all 0s to all 1 s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. noise spectral density (nsd) nsd is a measurement of the internally generated random noise. random noise is characterized as a spectral density. it is measured, in nv/hz, by loading the dac to midscale and measuring noise at the output. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change (or soft power - down and power - up) on one dac while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to lo ad current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is mea sured in standalone mode and expressed in nv -s ec . analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full - scale code change (all 0s to all 1s and vice versa) . then execut e a soft - ware ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv - sec.
ad5689/AD5687 data sheet rev. 0 | page 16 of 24 dac -to - dac crosstalk dac - to - dac c rosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is m easured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa), using the write to and update command s while monitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv -s ec . multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full - scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) thd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db.
data sheet ad5689/AD5687 rev. 0 | page 17 of 24 theory of operation digital - to - analog converter s (dacs) t he ad5689 / AD5687 are dual 16 - /12 - bit, serial input, voltage output dacs . the parts operate from supply voltages of 2.7 v to 5.5 v. data is written to the ad5689 / AD5687 in a 24- bit word format via a 3 - wire serial interface. the devices incorporate a power - on reset circuit to ensure that the dac output powers up to a known output state. the ad5689 / AD5687 also have a software power - down mode that reduces the typical current consumption to 4 a . transfer function because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n ref out d gainvv 2 where: gain is the output amplifier gain and is set to 1 by default. it can be set to 1 or 2 using the g ain select pin. wh en the gain pin is tied to gnd, both dacs output a span from 0 v to v ref . if the gain pin is tied to v logic , both dacs output a span of 0 v to 2 v ref . d is the decimal equivalent of the binary code that is loaded to the dac register as follows: 0 to 4,095 for the 12 - bit device and 0 to 65,535 for the 16 - bit device . n is the dac resolution. dac architecture the dac architecture consists of a string dac followed by an output amplifier. figure 36 shows a block diagram of the dac arc hitecture. figure 36 . single dac channel architecture block diagram the resistor string structure is shown in figure 37 . it is a string of resistors, each of value r. the code loaded to the dac register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. figure 37 . resistor string structure output amplifier s the output buffer amplifier can generate rail - to - rail voltages on its output, which gives an output range of 0 v to v dd . the actual range depends on the value of vref, the gain pin, the offset error, and the gain error. the gain pin selects the gain of the output, a s follows: ? if the gain pin is tied to gnd, both dac outputs have a gain of 1, and the output range is 0 v to v ref . ? if the gain pin is tied to v logic , both dac outputs have a gain of 2, and the output range is 0 v to 2 v ref . the se amplifier s are capable of driving a load of 1 k? in parallel with 2 nf to gnd. the slew rate is 0.8 v/s with a ? to ? scale settling time of 5 s. input register dac register resistor string ref (+) v ref gnd ref (?) v out x gain (gain = 1 or 2) 1 1255-036 r r r r r to output amplifier v ref 1 1255-037
ad5689/AD5687 data sheet rev. 0 | page 18 of 24 serial interface t he ad5689 / AD5687 have a 3 - wire serial interface ( sync , sclk, and s din) that is compatible with spi, qspi ? , and microwire ? interface stan dards as well as most dsps. see figure 2 for a timing diagram of a typi cal write sequence. the ad5689 / AD5687 contain an sdo pin that allows the user to daisy - chain multiple devices together (see the daisy - chain operation section) or read back data. input shift register the input shift register of the ad5689 / AD5687 is 24 bits wide, and data is loaded msb first (db23). the first four bits are the command bits, c3 to c0 (see table 9 ), followed by the 4 - bit dac address bits, composed of dac b, dac a , and two dont care bits set to 0 (see table 8 ). finally, the data - word completes the input shift register. the data - word comprises 16 - bit or 12 - bit input code, followed by zero dont care bits f or the ad5689 or four dont care bits for the AD5687 , as shown in figure 38 and figure 39 , respectively. these data bits are transferred to the input shift register on the 24 falling edges of sclk and updated on the rising edge of sync . comm ands can be executed on individual dac channels or on both dac channels, depending on the address bits selected . table 8. address commands address (n) selected dac channel dac b 0 0 dac a 0 0 0 1 dac a 1 0 0 0 dac b 1 0 0 1 dac a and dac b table 9 . command definitions command c3 c2 c1 c0 description 0 0 0 0 no operation 0 0 0 1 write to input register n (dependent on ldac ) 0 0 1 0 update dac register n with contents of input register n 0 0 1 1 write to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software reset (power - on reset) 0 1 1 1 reserved 1 0 0 0 set up dcen register (daisy - chain enable) 1 0 0 1 set up readback register (readback enable) 1 0 1 0 reserved reserved 1 1 1 1 reserved figure 38 . ad5689 input shift register content figure 39 . AD5687 input shift register content address bits command bits dac b 0 0 dac a d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 c2 c1 c0 db23 (msb) db0 (lsb) data bits 1 1255-038 address bits command bits dac b 0 0 dac a d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x c3 c2 c1 c0 db23 (msb) db0 (lsb) data bits 1 1255-039
data sheet ad5689/AD5687 rev. 0 | page 19 of 24 standalone operation the write sequence begins by bringing the sync line low. data from the sdin line is clocked into the 24 - bit input shift regis ter on the falling edge of sclk. after the last of 24 data b its is clocked in, sync is brought high. the programmed function is then executed; that is, an ldac - dependent change in dac register contents and/or a change in the mode of operation occurs. if sync is taken high before the 24 th clock, it is considered a valid frame and invalid data may be loaded to the dac. sync must be brought high for a minimum of 20 n s (single channel, see t 8 in figure 2 ) before the next write sequence so that a falling edge of sync can initiate the next write sequence. idle sync at the rails between write sequences for an even lower power operation of the part. t he sync line is kept low for 24 falling edges of sclk, and the dac is updated on the rising edge of sync . when the data has been transferred into the input register of the address ed dac, both dac registers and outputs can be updated by taking ldac low while the sync line is high. write and update com mands write to input register n (dependent on ldac ) command 0001 allows the user to write to the dedicated input register of each dac individually. when ldac is low, the input register is transparent (if not controlled by the ldac mask register). update dac register n with contents of input register n command 0010 loads the dac registers/outputs with the contents of the input registers selected and update s the dac outputs directly. write to and update dac channel n (independent of ldac ) command 0011 a llows the user to write to the dac registers and update the dac outputs directly. daisy - chain operation for systems that contain several dacs , the sdo pin can be used to daisy - chain several devices together. sdo is enabled through a software executable dai sy- chain ena ble (dcen) command. command 1000 is reserved for this dcen function (see table 9 ). daisy - chain mode is enabled by setting bit db 0 in the dcen register. th e default setting is standalone mode, where db0 (lsb) = 0. table 10 shows how the state of the bit corresponds to the mode of operation of the device. table 10 . daisy - chain enable ( dcen) register db0 (lsb) description 0 standalone mode (default) 1 dcen mode figure 40 . daisy - chaining multiple ad5689 / AD5687 devices the sclk pin is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the input shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the s din input on the next dac in the chain, a daisy - chain interface is constructed. ea ch dac in the system requires 24 clock pulses. t herefore, the total numb er of clock cycles must equal 24 n, where n is the total numbe r of devices that are updated. if sync is taken high at a clock that is not a multiple of 24, it is considered a valid frame and invalid data may be loaded to the dac . when the serial transfer to all devices is complete, sync is taken high . this latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. the serial clock can be continuous or a gated clock. a continuous sclk source can b e used only if sync can be held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the fin al clock to latch the data. 68hc11* miso sdin sclk mosi sck pc7 pc6 sdo sclk sdo sclk sdo sdin sdin sync sync sync ldac ldac ldac ad5689/ AD5687 ad5689/ AD5687 ad5689/ AD5687 *additional pins omitted for clarity. 1 1255-040
ad5689/AD5687 data sheet rev. 0 | page 20 of 24 readback operation readback mode is invoked through a software executable readback command. if the sdo output is disabled via the daisy - chain mode disable bit in the control register, it is automatically enabled for the duration of the read operation, after which it is disabled again. command 1001 is reserved for the readback function. this command, in association with selecting one of the address bits , dac b or dac a , select s the registe r to be read. note that only one dac register can be selected during readback. the remaining three address bits (which include the two dont care bits) must be set to logic 0 . the remaining data bits in the write sequence are ignored. if more than one addr ess bit is selected or no address bit is selected , dac channel a is read back by default. during the next spi write, the data that appears on the sdo output contains the data from the previously addressed register. for example, to read back the dac registe r for channel a, implement the following sequence: 1. write 0x900000 to the ad5689 / AD5687 input register. this setting configures the part for read mode with the channel a dac register selected. note that all data bits , db15 to db0 , are dont care bits. 2. follow this write operation with a second write, a nop condition, 0x000000. during this write, the data from the register is clocked out on the sdo line . db23 to db20 cont ain undefined data , and the last 16 bits contain the db19 to db4 dac register contents. power - down operation the ad5689 / AD5687 contain three separate power - down modes. command 0100 controls the power - down function (see table 9 ). these power - down modes are software - programmable by setting eight bit s, bit db7 to bit db0 , in the input shift register. there are two bits associated with each dac channel. table 11 explain s how the state of the two bits corresponds to the mode of operation of the device. either or both dacs (dac b, dac a ) can be powered down to the selected mode by setting the corresponding bits. see table 12 for the contents of the input shift register during the power - down/ power - up operation. table 11 . modes of operation operating mode pdx1 pdx0 normal operation mode 0 0 power - down modes 1 k to gnd 0 1 100 k to gnd 1 0 three - state 1 1 when both bit pdx1 and bit pdx0 (where x is the channel that is selected) in the input shift register are set to 0, the part s work normally , with a normal power consumption of 4 ma at 5 v. however, for th e three power - down modes of the ad5689 / AD5687 , the supply current falls to 4 a at 5 v. not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values . this switchover has the advantage that the output impedance of the part is known while the part is in power - down mode. the three power - down options are as follows: ? t he output is connected internally to gnd through a 1 k? resistor. ? the output is connected internally to gnd through a 100 k? resistor. ? the output is left open - circuited (three - state). the output stage is illustrated in figure 41. figure 41 . output stage during power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power - down mode is activated. however, the contents of the dac register are unaffected when in power - down, and t he dac register can be updated while the device is in power - down mode. the time that is required to exit power - down is typically 4.5 s for v dd = 5 v table 12 . 24- bit input shift register contents of power - down/power - up operation 1 db23 (msb) db2 2 db2 1 db20 db19 to db16 db15 to db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) 0 1 0 0 x x pdb1 pdb0 1 1 1 1 pda1 pda0 command bits (c3 to c0) address bits; dont care power - down, select dac b set to 1 set to 1 power - down, select dac a 1 x = dont care. resistor network v out x dac power-down circuitry amplifier 1 1255-041
data sheet ad5689/AD5687 rev. 0 | page 21 of 24 load dac ( hardware ldac pin ) the ad5689 / AD5687 dacs have double buffered interfaces consisting of two banks of registers: input registers and dac registers. the user can write to any combination of the input registers. updates to the dac register are controlled by the ldac pin. figure 42 . simplified diagram of input loading circuitry for a single dac instantaneous dac updating ( ldac held low ) ldac is held low while data is clocked into the input register using command 0001. both t he addressed input register and the dac register are updated on the rising edge of sync , and then the output begins to change (see table 14 and table 15). deferred dac updating ( ldac pulsed low) ldac is held high while data is clocked into the input register using command 0001 . both dac outputs are asynchronously updated by taking ldac low after sync is taken high. the update then occurs on the falling edge of ldac . ldac mask register command 0101 is reserved for a software ldac mask function, which allows the address bits to be ignored. a write to the dac using command 0101 loads the 4 - bit ldac mask register (db3 to db0). the default setting for each channel is 0; that is, the ldac pin works normally. setting the selected bit to 1 fo rces the dac channel to ignore transitions on the ldac pin, regardless of the state of the hardware ldac pin. this flexibility is use ful in applications where the user wishes to select which channels respond to the ldac pin. the ldac mask register gives the user extra flexibility and control over the hardware ldac pin (see table 13 ). setting an ldac bit (db3, db0 ) to 0 for a dac channel means that the update of this channel is controlled by the hardware ldac pin. table 13. ldac overwrite definition load ldac register ldac bits (db3, db0) ldac pin ldac operation 0 1 or 0 determined by the ldac pin. 1 x 1 dac channels update and override the ldac pin. dac channels see the ldac pin as set to 1. 1 x = dont care. table 14 . 24- bit input shift register contents for ldac operation 1 db 23 (msb) db22 db21 db20 db19 db18 db17 db16 db 15 to db4 db3 db2 db1 db 0 (lsb) 0 0 0 1 x x x x x dac b 0 0 dac a command bits (c3 to c0) address bits , d ont care dont care setting the ldac bit to 1 overrides the ldac pin 1 x = dont care. table 15. write commands and ldac pin truth table 1 command description hardware ldac pin state input register contents dac register contents 0001 write to input register n (d ependent on ldac ) v logic data update no change (no update) gnd 2 data update data update 0010 upda te dac register n with contents of input register n v logic no change updated with input register contents gnd no change updated with input register contents 0011 write to and update dac channel n v logic data update data update gnd data update data update 1 a high - to - low hardware ldac pin transition always updates the contents of the dac register with the contents of the input register on channels that are not mas ked (blocked) by the ldac mask register. 2 when the ldac pin is permanently tied low, the ldac mask bits are ignored. sync sclk v out x dac register interface logic output amplifier ldac sdo sdin v ref input register 16-/12-bit dac 1 1255-042
ad5689/AD5687 data sheet rev. 0 | page 22 of 24 hardware reset ( reset ) reset is an active low reset that allows the outputs to be cleared to either zero scale or midscale. the clear code value is user selectable via the power - on reset select pin (rstsel). reset must be kept low for a minimum amount of time to complete the operation (see figure 2 ). when the reset signal is returned high, the outpu t remains at the cleared value until a new value is programmed. the outputs cannot be updated with a new value while the reset pin is low. there is also a software executable reset function that resets the dac to the power - on reset code. command 0110 is designated for this software reset function (see table 9 ). any events on ldac or reset during a power - on reset are ignored . reset select pin (rs tsel) th e ad5689 / AD5687 contain a power - on reset circuit that controls the output voltage durin g power - up. when the rstsel pin is connected low (to gnd), the output powers up to zero scale. note that this is outside the linear region of the dac. when the rstsel pin is connected high (to v logic ), v out x powers up to midscale. the output remains powered up at this level until a valid wr ite sequence is sent to the dac.
data sheet ad5689/AD5687 rev. 0 | page 23 of 24 applications informa tion microprocessor inter facing microproc essor interfacing to the ad5689 / AD5687 is achieved via a serial bus using a standard protocol that is compatible with dsp processors and microcontrollers. the communications channel requires a 3 - wire or 4 - wire interface consisting of a clock sig nal, a data signal, and a synchronization signal. each device require s a 24 - bit data - word with data valid on the rising edge of sync . ad5689 / AD5687 to adsp - bf531 interface the spi interface of the ad5689 / AD5687 is designed to be easily connected to industry - standard dsps and microcontrollers. figure 43 shows the ad5689 / AD5687 connected to an analog devices blackfin? dsp. the blackfin has an integrated spi port that connects directly to the spi pins of the ad5689 / AD5687 . figure 43 . adsp - bf531 interface to the ad5689 / AD5687 ad5689 / AD5687 to sport interface the analog devices adsp - bf527 has one sport serial port. figure 44 shows how one sport interface can be used to control the ad5689 / AD5687 . figure 44 . sport interface to the ad5689 / AD5687 layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. design the pcb on which the ad5689 / AD5687 are mounted so that the ad5689/ AD5687 lie on the analog plane. provide the ad5689 / AD5687 with ample supply bypassing of 10 f in parallel with 0.1 f on each supply, located as close to the package as possible, ideally right up against the device. the 10 f capacitor is of the tantalum bead type. use a 0.1 f capa - citor with low effective ser ies resistance (esr) and low effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. in systems where there are man y devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. each ad5689 or AD5687 has an exposed paddl e beneath the device. connect this paddle to the gnd supply for the part. for optimum performance, use special considerations to design the motherboard and to mount the package. for enhanced thermal, electrical, and board level performance, solder the expo sed paddle on the bottom of the package to the corresponding thermal land paddle on the pcb. design thermal vias into the pcb land paddle area to further improve heat dissipation. the gnd plane on the device can be increased (as shown in figure 45 ) to provide a natural heat sinking effect. figure 45 . paddle connection to board galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barr ier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazar dous common - mode voltages that may occur. the i coupler? products from analog dev ices provide voltage isolation in excess of 2. 5 kv. the serial loading struc ture of the ad5689 / AD5687 makes the se part s ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 46 shows a 4 - channel isolated interface to the ad5689 / AD5687 using an adum1400 . for more information, visit www.analog.com/icouplers . figure 46 . isolated interface adsp-bf531 sync spiselx sclk sck sdin mosi ldac pf9 reset pf8 ad5689/ AD5687 1 1255-043 adsp-bf527 sync sport_tfs sclk sport_tsck sdin sport_dto ldac gpio0 reset gpio1 ad5689/ AD5687 1 1255-044 ad5689/ AD5687 gnd plane board 1 1255-045 encode serial clock in controller adum1400 1 serial data out sync out load dac out decode to sclk to sdin to sync to ldac v ia v oa encode decode v ib v ob encode decode v ic v oc encode decode v id v od 1 additional pins omitted for clarity. 1 1255-046
ad5689/AD5687 data sheet rev. 0 | page 24 of 24 outline dimensions figure 47. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very very thin quad (cp-16-22) dimensions shown in millimeters figure 48. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model 1 resolution temperature range accuracy pa ckage description packageoption branding ad5689bcpz-rl7 16 bits ?40c to +105c 2 lsb inl 16-lead lfcsp_wq cp-16-22 dkw ad5689bruz 16 bits ?40c to +105c 2 lsb inl 16-lead tssop ru-16 ad5689bruz-rl7 16 bits ?40c to +105c 2 lsb inl 16-lead tssop ru-16 AD5687bcpz-rl7 12 bits ?40c to +105c 1 lsb inl 16-lead lfcsp_wq cp-16-22 dl0 AD5687bruz 12 bits ?40c to +105c 1 lsb inl 16-lead tssop ru-16 AD5687bruz-rl7 12 bits ?40c to +105c 1 lsb inl 16-lead tssop ru-16 1 z = rohs compliant part. 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d11255-0-2/13(0)

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